The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to device structures for a vertical field-effect transistor and methods of fabricating a vertical field-effect transistor.
Traditional complementary metal-oxide-semiconductor (CMOS) structures for a field-effect transistor include a source, a drain, a channel situated between the source and drain, and a gate electrode configured to respond to a gate voltage by selectively connecting the source and drain to each other through the channel. Field-effect transistor structures can be broadly categorized based upon the orientation of the channel relative to a surface of a semiconductor substrate with which they are formed. In a vertical field-effect transistor, the channel is located in a semiconductor fin that projects in the vertical direction from the surface of the semiconductor substrate. The source and the drain are arranged at the top and bottom of the semiconductor fin. The direction of the gated current flow in the channel between the source and drain is generally perpendicular (i.e., vertical) to the substrate surface and parallel to the height of the fin.
The gate length of a vertical field-effect transistor is defined by depositing gate material between semiconductor fins and then recessing the gate material to a given height relative to the top surface of the semiconductor fins. The etch-back process used to recess the gate material can introduce variations in the gate length among the different vertical field-effect transistors due to variations in the etching process.